Space and/or military operating environments for semiconductor devices (for example, CMOS devices) require that the transistors of these devices be resistant to radiation. Exposure to radiation can cause conventional devices, which are not radiation-hard to malfunction or destruct. It is recognized [6] that resistance to can be improved by fabricating devices on silicon-on-insulator (SOI) substrates. The small volume of silicon in the SOI layer improves the resistance to radiation-induced single-event upset. In addition, latch-up paths between adjacent devices (i.e., transistors) which are present in conventional bulk-semiconductor devices are eliminated in the SOI devices.
Although SOI technology has many advantages, it is a disadvantage relative to bulk silicon for hardness against total dose radiation [6]. The presence of the buried insulator layer creates an additional oxide that must be hardened. Because of its big thickness, sufficient amounts of positive charge are trapped in the buried insulator following total dose radiation. The charge accumulation results in increased device leakage and threshold voltage shifts.
Several methods of improving the total radiation dose hardness for SOI circuits are known. These techniques include the use of thicker silicon films and employing thinner buried oxides [5]. Due to the cited above review paper [6] by Johnson, partially depleted SOI devices have better radiation hardness than the fully depleted SOI. Thicker silicon films improve the total dose hardness because the film is only partially depleted. Thus, the gate charge is not coupled to the buried oxide charge.
This approach has the significant drawback that the body of the transistor is neutral and has a floating electrical potential. These results in the turn-on of the parasitic bipolar transistor formed by the source/body/drain of the device. To minimize the leakage caused by the transistor, the body of the transistor must be grounded either by a separate contact, or by a strap to the source. However, this results in a technology that is not compatible with bulk VLSI designs. Furthermore, many of the benefits of SOI, such as high transconductance, sharp transistor turn-on slopes, low power consumption, high speed action, shortened fabrication process, and circuit density improvements are lost with partially depleted SOI.
Another radiation hardening approach is to use thinner buried oxides [5]. However, in fully depleted structures, the front gate threshold voltage is capacitively coupled to the buried oxide [6]. Thus, thinning the buried oxide reduces the amount of charge that it traps, however, its capacitance goes up proportionally. Thus, essentially the same voltage shift is seen by the front gate.
In previous art, a method of forming a radiation hardened SOI structure is known due to U.S. Pat. No. 5,795,813 [1] by Hughes. Buried oxide of SOI is hardened. The radiation hardening is done by implantation of impurities that form recombination centers in the oxide. All the radiation hardening is done prior to the bonding of the device silicon layer. It prevents damage of the silicon device layer by the hardening process.
This conventional method is not effective enough. Under irradiation, holes and electrons are generated in the oxide. Then, electrons continue moving and they leave the oxide. Holes are not mobile and they are kept in the oxide. That holes cannot disappear on the recombination centers because of lack of electrons for them and because of lack of mobility. Holes remain in the oxide thus building up the positive charge.
A conventional radiation-hard, semiconductor device of SOI CMOS type is known according to U.S. Pat. No. 5,807,771 [2] by Vu et al. The radiation-hard semiconductor device includes heavy doped buried n-type and p-type wells in a first silicon layer over an insulator. Over the insulator, a second silicon layer is formed with congruent lightly-doped n-type and p-type layers in which complementary MOSFET active devices are formed. The heavy wells improve resistance to back-channel radiation-induced leakage due to (1) partially-depleted regime ensured by the heavy wells, and (2) gettering function of the wells. The gettering mostly prevents yield drop, but it also affects indirectly on the radiation hardness of the SOI. The final SOI devices have more uniform characteristics from device to device. Integrated semiconductor device fails under irradiation upon fail of the weakest from the devices. The uniform characteristics mean absence of weak devices.
A disadvantage of this process is that it improves only semiconductor part of the integrated semiconductor device while the final radiation hardness is limited by the dielectric parts of the integrated semiconductor device.
A process for preventing yield drop in fabrication of SOI semiconductor devices due to heavy metal contamination is described in U.S. Pat. No. 5,753,560 [3] by Hong. The process uses lateral gettering of the contaminants.
Disadvantage of the process [3] is that gettering technique used is not effective enough. Lateral gettering is not as effective as proximity gettering. In addition, lateral gettering has an inherent drawback because forming of special areas in SOI top film are required. That special areas work as a getter. It decrease the maximum achievable packing density of transistors, increase number of processing steps, and fabrication costs.
As it was mentioned above, the gettering improves the radiation hardness indirectly. The performance of a semiconductor device is affected by impurities in the semiconductor substrate on which the semiconductor device is fabricated. For example, the presence of metallic impurities such as copper, nickel, iron, chromium, molybdenum, etc. tends to introduce generation-recombination centers in the energy band gap and degrade the integrity of the oxide layer formed on the semiconductor substrate, thereby affecting the performance of the semiconductor device. Impurity gettering can be performed to reduce impurities in a region of the semiconductor substrate where the semiconductor device is fabricated. Conventionally, impurity gettering includes intrinsic gettering and extrinsic gettering processes as it is described in a book Gettering and Defect Engineering in Semiconductor Technology by Herbert P. Richter, Enfield Publishers, 660 pages, 1992. In an intrinsic gettering process, gettering sinks, such as crystal defects or oxygen precipitates, are formed in the semiconductor substrate at a distance from the front side of the substrate, wherein the distance is greater than the depth of semiconductor devices fabricated in the substrate. The substrate is heated to aid the diffusion of impurities in the substrate. As the impurities diffuse, they are trapped or absorbed by the gettering sinks. In an extrinsic gettering process, a gettering sink, such as a polycrystalline silicon layer, is formed on the backside of the substrate. The semiconductor substrate is heated to aid the diffusion of impurities in the substrate. As the impurities diffuse, they are trapped or absorbed by the gettering sink formed on the backside. Therefore, after either the intrinsic or the extrinsic process, the impurity concentration near the front side of the substrate decreases.
However, the gettering processes described in the cited book Gettering and Defect Engineering in Semiconductor Technology by Herbert P. Richter, Enfield Publishers, 660 pages 1992 are designed for bulk silicon substrates. They are ineffective for a semiconductor-on-insulator substrate. A semiconductor device fabricated on a SOI substrate typically extends from the front side of the substrate to the buried insulator layer. Accordingly, the gettering sinks, either intrinsic or extrinsic, are formed below the buried insulator layer, which is a diffusion barrier to some impurities in the substrate. In a conventional fabrication process in which the temperature of the substrate reaches approximately 1000xc2x0 C., the diffusivities of some impurities, such as iron, chromium, molybdenum, etc., are not high enough to overcome the diffusion barrier and reach the gettering sink below the buried insulator layer. These impurities remain in an active region of the substrate and may affect the performance of a semiconductor device fabricated therein.
Accordingly, it would be advantageous to getter heavy metal impurities introduced during fabrication of semiconductor-on-insulator devices. It is desirable for the method to effectively remove impurities from the region in a semiconductor-on-insulator substrate where a semiconductor device is formed (i.e., from top silicon). It is also desirable for the method to enhance the integrity of gate oxide of an insulated gate semiconductor device fabricated on SOI.
In the prior art, a process for fabrication of SOI wafers is known due to U.S. Pat. No. 5,374,564 [4] by Bruel. It comprises subjecting a semiconductor wafer to the 4 following stages: (1) implantation by bombardment of the face of the said wafer by means of ions creating in the volume of said wafer a layer of gaseous microbubbles defining in the volume of said wafer a lower region constituting the mass of the substrate and an upper region constituting the thin film; (2) intimately contacting the planar face of said wafer with a stiffener constituted by a rigid material layer; (3) annealing the assembly of said wafer and said stiffener at a temperature above that at which the ion bombardment was carried out and sufficient to create by a crystalline rearrangement effect in said wafer and a pressure effect in the said microbubbles, a separation between the thin film and the mass of the substrate; (4) 1100xc2x0 C. annealing to strengthen bonds between stiffener and the delaminated layer. The process due to [4] is known as a SmartCut(trademark) process xe2x80x9cWafer bonding and SmartCut for formation of silicon-on-insulator materialsxe2x80x9d by S. Bengtsson, in Proceedings of 5th Int. Conf. on Solid-State and Integrated Circuit Technology, 1998, pp.745-748 [8]. This process is also known as H2-Split Process xe2x80x9cInternational Technology Roadmap for Semiconductorsxe2x80x9d, 1999 Edition, P-115 [10].
A disadvantage of the process [4] is that the buried oxide is not radiation hard due to its damage during 1100xc2x0 C. annealing. The fundamental reason of deteriorating of the radiation hardness by the buried oxides is losing of oxygen from initially stoichiometric buried silicon dioxide. Temperature of 1100xc2x0 C. is high enough to initiate oxygen diffusion in the silicon dioxide, so the oxygen escapes from the buried oxide. The former oxygen sites become oxygen vacancies. The vacancies serve as hole traps in the oxide. They catch and keep positive charge under irradiation, making the buried oxide low radiation hard.
A process of radiation hardening a buried oxide in SOI is known in the prior art due to paper by Stahlbush [7]. The process uses a supplemental oxygen implantation into the buried oxide to compensate the oxygen deficiency that caused by high temperature annealing. High temperature annealing is required to form a SOI wafer with SIMOX technology.
A disadvantage of this method is that it is difficult to find an exact amount of oxygen needed to cover the oxygen deficiency. Therefore an improvement in total dose radiation hardness of final SOI based devices is not repeatable (it varies from wafer to wafer).
The description of prior art shows that it will be advantageously to simultaneously improve both the top silicon layer and the buried insulator of SOI to get a radiation hard SOI semiconductor devices. The top silicon can be improved by built-in getter, and the buried insulator can be improved by decreasing of trap for holes in the insulator.
The present invention relates to the fabrication of silicon-on-insulator (SOI) wafers and fabrication semiconductor devices on the SOI substrate. More particularly, the present invention relates to such SOI devices which are radiation-hard, resistant to hot-electron effects, and have built-in getter to increase yield.
An object for this invention is to get radiation hardened semiconductor devices on SOI substrate. Improvements of quality of the buried insulator of SOI cause the hardening. SOI wafer with high quality buried oxide is fabricated, then the semiconductor devices are fabricated on the wafer by process preserving high quality of the buried oxide.
Another object for this invention is to suppress hot electron degradation effects in semiconductor devices on SOI substrate. It is also caused by the improved quality (low trap density) of the buried oxide.
Yet another object for this invention is to increase yield of integrated semiconductor devices on SOI substrate by providing a gettering capability to top silicon layer of SOI. xc2xd Rp defects from hydrogen implantation works as proximity getters.
Yet another object of this invention is to increase radiation hardness of SOI devices by providing the xc2xd Rp defects in active areas of the SOI devices where these defects work as sinks for primary radiation-induced defects (vacancies and interstitials).
Improvements of quality of the buried oxide of SOI and attaining a gettering capabilities to the top silicon layer cause the hardening. SOI wafer with high quality buried oxide and with getter is fabricated, then the semiconductor devices are fabricated on the wafer by a process preserving high quality of the buried oxide and preserving the getter.
The objects of the invention listed above are achieved by fabrication of SOI wafer with H2-split process sequence and processing temperature of 4th step of the process limited to 900xc2x0 C. and subsequent fabrication of semiconductor devices on that substrate with process temperatures limited to 900xc2x0 C.
Limiting of temperature to the above-indicated value preserves stoichiometric silicon dioxide in buried insulator layer. Oxygen does not out-diffuse from the silicon dioxide at temperatures lower than 900xc2x0 C. Accordingly, oxygen vacancies are not formed in the buried insulator. The oxygen vacancies in silicon dioxide are traps for holes. Under irradiation, electrons and holes are generated in the oxide. Electrons leave the oxide and holes are accumulated in the oxide on the traps. The trapped holes build a positive charge in the oxide. The positive charge causes shifts of threshold voltages of transistors fabricated above the buried oxide. The shifts cause failures of semiconductor device operation. Accordingly, preventing of oxygen out-diffusion preserves high total dose radiation hardness of semiconductor devices made on SOI.
Also, limiting of temperature to the indicate d value during semiconductor process fabrication preserves xc2xd Rp defects in top silicon layer of SOI. The xc2xd Rp defects are dislocation microloops. They are formed from initially displaced atoms of silicon lattice. Processing of SOI structures at elevated temperatures transforms the initial displacements into the xc2xd Rp defects. The initial displacements are caused by hydrogen implantation at the 1st step of the H2 split process. Heating the silicon structure with displacements transforms the displacements into secondary radiation-induced defects. Further heating transforms the secondary defects with annealing out of less thermally stable ones and forming more thermally stable ones. Total number of the secondary defects decrease with increasing of the anneal temperature. Heating over 900xc2x0 C. anneals out all the secondary defects. The dislocation microloops are the most thermally stable among the secondary defects. The xc2xd Rp defects getter heavy metal impurities that are introduced into the SOI semiconductor devices during every step of the device fabrication process. The heavy metal contamination in semiconductor devices causes their inoperability. After trapping on getters the heavy metal contaminants does not deteriorate the device operation. Accordingly, the invention allows increasing yield of devices on SOI.